Quantum Error Correction on a Hexagonal Lattice
Quantum computing has been making strides in recent years, with researchers continuously seeking innovative ways to improve the reliability and efficiency of quantum processors. A recent development from our team focuses on optimizing quantum error correction using a hexagonal lattice configuration in our Willow architecture. This breakthrough could pave the way for more efficient quantum computing solutions.
The Willow Architecture and Its Challenges
In the current Willow architecture, each physical qubit is connected to its four nearest neighbors, forming a square lattice. While this arrangement facilitates gate operations between neighboring qubits, it introduces certain design constraints. Specifically, the need for additional wiring to control couplers between qubits can increase complexity and cost. The pursuit of a more streamlined design led our team to explore the potential of a hexagonal lattice.
Advantages of a Hexagonal Lattice
Transitioning to a hexagonal lattice allows each qubit to connect to just three neighbors instead of four, thus simplifying the design and manufacturing process. This configuration not only improves hardware performance but also reduces the complexity of the optimization algorithms used for qubit and gate frequency selection. The result is a 15% improvement in the simulated error suppression factor, highlighting the potential benefits of a hexagonal lattice.
Implementing Error Correction with Dynamic Circuits
To achieve error correction with only three couplers per qubit, we employ dynamic circuits with two distinct types of error correction cycles. Each cycle utilizes three couplers per qubit, with one coupler used twice during the cycle. This approach results in a quantum error correction circuit with dynamic, overlapping detection regions, enabling effective error triangulation while maintaining the reduced coupler requirement.
Evaluation and Results
We evaluated this three-coupler error correction circuit on our Willow processor, which features square-shaped connectivity. By disabling all unused couplers, we simulated the performance of hex connectivity. Our findings reveal that as the code distance increases from 3 to 5, the logic error rate improves by a factor of 2.15. This performance matches that of a traditional solid-state circuit running on the same hardware, as demonstrated in our landmark experiment last year.
The Road Ahead
Our results demonstrate the feasibility of constructing a hexagonal qubit array for quantum error correction, a design space that has been extensively studied in simulation. The adoption of a hexagonal lattice offers significant advantages in terms of design simplification and performance enhancement, positioning it as a promising avenue for future quantum processor development.
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